1. Field of the Invention
The present invention relates to an electrical interconnection arrangement for making connection between electronic devices and, more particularly, to making electrical connection between chip die and the next level of carrier.
2. Background and Related Art
One of the problems encountered with some semiconductor chip die connections to the next level of packaging is the high stress on the interconnections caused by coefficient of thermal expansion (CTE) mismatch. The CTE thermal mismatch is particularly large where the chip die is connected to laminate chip carriers made of material similar to an epoxy circuit board material. As circuit densities in chip dies increase, so does the heat generated by these dies thereby compounding the problem with larger temperature variations in its thermal cycle. In addition, certain applications, such as flip chip applications, have required encapsulation to ensure a reliable flip chip interconnection in the solder joints. Such encapsulation typically employs a high strength epoxy which acts to bond the chip die to the laminate chip carrier. This bonding of chip die to chip carrier reduces solder joint stress during thermal cycling but causes the chip die itself to be put under cyclical high internal stress eventually leading to chip cracking, delamination and device breakdown.
The above described high internal stresses on the chip die are generally attributed to the fact that the bonding of chip die to laminate chip carrier acts to cause this composite of materials to act like a xe2x80x9cbimetallicxe2x80x9d element wherein the composite bends upon heating due to the different CTE of the materials. As a result of the large thermal mismatch between the die and laminate chip carrier, the cyclical bending over time causes device failure. In this regard, the CTE for a typical chip die may be in the order of 3 micro inches per inch per degree Centigrade while a typical late chip carrier is around six times that amount. Thus, although the use of encapsulation is to prevent the C-4 connections from detaching from fatigue and fracturing over thermal cycling, the bonding action of the encapsulation in itself acts to cause the chips to fracture and separate from the chip carrier.
In general, others have attempted to address the problems caused by CTE mismatch of materials in IC packaging by providing various interposing structures that attempt to reduce the mismatch of CTE. For example, multiple layers of materials with varying CTEs may be employed to form an interposing layer between one level of packaging and the next, with the layers having a gradation of CTEs such that the layer contacting one level of packaging is selected to have a CTE which more closely matches the CTE of that level while the layer contacting the next level of packaging has a CTE more closely matching that level while layers between may gradually reduce the difference. In addition, efforts have also been made to use interposing layers which are flexible in nature such as to reduce the stress on electrical interconnections during thermal cycling created by thermal mismatch. However, these various efforts typically rely on single or multiple layers of material which are either costly to fabricate or difficult to assemble, and are not totally effective in their purpose. More often, these layers are between ceramic chip carriers and circuit board or card.
In accordance with the teachings of the present invention, internal stresses in chip dies and their electrical interconnection caused by encapsulation and bonding of chip dies to laminate chip carriers are overcome through the use of a floating interposer having an array of connectors extending therethrough and positioned between chip die contacts and circuit card contacts. The floating interposer acts as chip carrier and provides stress relief to the electrical interconnections between chip die and circuit card by moving on its opposing surfaces relative to the CTE rate of the material with which it is in contact.
The floating interposer of the present invention comprises a flexible and compliant layer of low modulus material having an array of vias plated with copper which vias terminate in copper pads at each end on opposing surfaces of the flexible layer. In addition, the flexible layer may have an array of relatively large holes arranged between the array of vias to produce a xe2x80x9cswiss-cheese-likexe2x80x9d structure to give more resilience.
In one fabrication process, when the plated vias of the interposer are aligned with C-4 solder balls on a flip chip die, upon heating the vias become filled with solder while becoming electrically connected to the chip die. The other ends of the vias are attached to the circuit card by a low melt solder. Alternatively, the flexible interposer may be copper plated directly against the BLM pads on the chip die.
Accordingly, it is an object of the present invention to provide an improved integrated circuit device package and method of making same.
It is another object of the present invention to provide improved electronic device interconnection and method of making same.
It is a further object of the present invention to provide improved electronic interconnection between chip die device and chip carrier.
It is yet a further object of the present invention to provide an improved electronic interconnection between chip die and chip carrier such as to reduce internal stress in both the chip die and the electrical interconnections between chip die and chip carrier.
It is still yet a further object of the present invention to provide a flexible interposer arrangement between chip die and chip carrier which allows the chip die to be connected to the chip carrier without encapsulation of the interconnection points.
It is another object of the present invention to provide a method and apparatus for making electrical interconnection between chip die directly to circuit card.
It is yet another object of the present invention to provide a compact, reworkable die solution.